? semiconductor components industries, llc, 2011 june, 2011 ? rev. 5 1 publication order number: NB4N527S/d NB4N527S 3.3v, 2.5gb/s dual anylevel ? to lvds receiver/driver/buffer/ translator with internal input termination NB4N527S is a clock or data receiver/driver/buffer/translator capable of translating anylevel tm input signal (lvpecl, cml, hstl, lvds, or lvttl/lvcmos) to lvds. depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 gb/s or 1.5 ghz, respectively. the NB4N527S has a wide input common mode range of gnd + 50 mv to v cc ? 50 mv combined with two 50 internal termination resistors is ideal for translating differential or single ? ended data or clock signals to 350 mv typical lvds output levels without use of any additional external components (figure 6). the device is offered in a small 3 mm x 3 mm qfn ? 16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements. application notes, models, and support documentation are available on www.onsemi.com. ? maximum input clock frequency up to 1.5 ghz ? maximum input data rate up to 2.5 gb/s (figure 5) ? 470 ps maximum propagation delay\ ? 1 ps maximum rms jitter ? 140 ps maximum rise/fall times ? single power supply; v cc = 3.3 v 10% ? temperature compensated tia/eia ? 644 compliant lvds outputs ? internal 50 termination resistor per input pin ? gnd + 50 mv to v cc ? 50 mv v cmr range ? these are pb ? free devices time (58 ps/div) figure 2. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv; input signal ddj = 14 ps) voltage (130 mv/div) device ddj = 10 ps a = assembly location l = wafer lot y = year w = work week = pb ? free package *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 9 of this data sheet. ordering information 16 nb4n 527s alyw 1 q0 q0 figure 1. functional block diagram vtd0 d0 q1 q1 d0 50 * d1 d1 vtd0 50 * 50 * 50 * vtd1 vtd1 1 *r tin (note: microdot may be in either location)
NB4N527S http://onsemi.com 2 figure 3. pin configuration (top view) gnd nc nc v cc vtd0 d0 d0 vtd0 q0 q0 q1 q1 v td1 d1 d1 v td1 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB4N527S exposed pad (ep) table 1. pin description pin name i/o description 1 vtd1 ? internal 50 termination pin for d1. (r tin ) 2 d1 lvpecl, cml, lvds, lvcmos, lvttl, hstl noninverted differential clock/data d1 input (note 1). 3 d1 lvpecl, cml, lvds, lvcmos, lvttl, hstl inverted differential clock/data d1 input (note 1). 4 vtd1 ? internal 50 termination pin for d1 . (r tin ) 5 gnd ? 0 v. ground. 6, 7 nc no connect. 8 v cc positive supply voltage. 9 q1 lvds output inverted d1 output. typically loaded with 100 receiver termination resistor across differential pair. 10 q1 lvds output noninverted d1 output. typically loaded with 100 receiver termination resistor across differential pair. 11 q0 lvds output inverted d0 output. typically loaded with 100 receiver termination resistor across differential pair. 12 q0 lvds output noninverted d0 output. typically loaded with 100 receiver termination resistor across differential pair. 13 vtd0 ? internal 50 termination pin for d0. 14 d0 lvpecl, cml, lvds, lvcmos, lvttl, hstl noninverted differential clock/data d0 input (note 1). 15 d0 lvpecl, cml, lvds, lvcmos, lvttl, hstl inverted differential clock/data d0 input (note 1). 16 vtd0 ? internal 50 termination pin for d0 . ep exposed pad. ep on the package bottom is thermally connected to the die improved heat transfer out of package. the pad is not electrically connected to the die, but is recommended to be soldered to gnd on the pcb. 1. in the differential configuration when the input termination pins(vtd0/vtd0 , vtd1/ vtd1 ) are connected to a common termination voltage or left open, and if no signal is applied on d0/d0 , d1/d1 input, then the device will be susceptible to self ? oscillation.
NB4N527S http://onsemi.com 3 table 2. attributes characteristics value moisture sensitivity (note 2) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in esd protection human body model machine model charged device model > 2 kv > 200 v > 1 kv transistor count 281 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.8 v v i positive input gnd = 0 v v i = v cc 3.8 v i in input current through r t (50 resistor) static surge 35 70 ma ma i osc output short circuit current line ? to ? line (q to q ) line ? to ? end (q or q to gnd) q or q to gnd q to q continuous continuous 12 24 ma t a operating temperature range qfn ? 16 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 41.6 35.2 c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 3) qfn ? 16 4.0 c/w t sol wave solder pb pb ? free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB4N527S http://onsemi.com 4 table 4. dc characteristics, clock inputs, lvds outputs v cc = 3.0 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c symbol characteristic min typ max unit i cc power supply current (note 8) 40 53 ma differential inputs driven single ? ended (figures 11, 12, 16, and 18) v th input threshold reference voltage range (note 7) gnd +100 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv differential inputs driven differentially (figures 7, 8, 9, 10, 17, and 19) v ihd differential input high voltage 100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v cmr input common mode range (differential configuration) gnd + 50 v cc ? 50 mv v id differential input voltage (v ihd ? v ild ) 100 v cc mv r tin internal input termination resistor 40 50 60 lvds outputs (note 4) v od differential output voltage 250 450 mv v od change in magnitude of v od for complementary output states (note 9) 0 1 25 mv v os offset voltage (figure 15) 1125 1375 mv v os change in magnitude of v os for complementary output states (note 9) 0 1 25 mv v oh output high voltage (note 5) 1425 1600 mv v ol output low voltage (note 6) 900 1075 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. lvds outputs require 100 receiver termination resistor between differential pair. see figure 14. 5. v oh max = v os max + ? v od max. 6. v ol max = v os min ? ? v od max. 7. v th is applied to the complementary input when operating in single ? ended mode. 8. input termination pins open, dx/dx at the dc level within v cmr and output pins loaded with r l = 100 across differential. 9. parameter guaranteed by design verification not tested in production.
NB4N527S http://onsemi.com 5 table 5. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v; (note 10) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin )f in 1.0 ghz (figure 4) f in = 1.5 ghz 220 200 350 300 220 200 350 300 220 200 350 300 mv f data maximum operating data rate 1.5 2.5 1.5 2.5 1.5 2.5 gb/s t plh , t phl differential input to differential output propagation delay 270 370 470 270 370 470 270 370 470 ps t skew duty cycle skew (note 11) within device skew (note 17) device ? to ? device skew (note 15) 8 5 30 45 25 100 8 5 30 45 25 100 8 5 30 45 25 100 ps t jitter rms random clock jitter (note 13) f in = 1.0 ghz f in = 1.5 ghz deterministic jitter (note 14) f data = 622 mb/s f data = 1.5 gb/s f data = 2.488 gb/s crosstalk induced jitter (note 16) 0.5 0.5 6 7 10 20 1 1 20 20 25 40 0.5 0.5 6 7 10 20 1 1 20 20 25 40 0.5 0.5 6 7 10 20 1 1 20 20 25 40 ps v inpp input voltage swing/sensitivity (differential configuration) (note 12) 100 v cc ? gnd 100 v cc ? gnd 100 v cc ? gnd mv t r t f output rise/fall times @ 250 mhz q, q (20% ? 80%) 60 100 140 60 100 140 60 100 140 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inppmin with 50% duty cycle clock source and v cc ? 1400 mv of fset. all loading with an external r l = 100 across ?d? and ?d ? of the receiver. input edge rates 150 ps (20% ? 80%). 11. see figure 13 differential measurement of t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform @ 250 mhz. 12. input voltage swing is a single ? ended measurement operating in differential mode. 13. rms jitter with 50% duty cycle input clock signal. 14. deterministic jitter with input nrz data at prbs 2 23 ? 1 and k28.5. 15. skew is measured between outputs under identical transition @ 250 mhz. 16. crosstalk induced jitter is the additive deterministic jitter to channel one with channel two active both running at 622 gb/ s prbs 2 23 ? 1 as an asynchronous signals. 17. the worst case condition between q0/q0 and q1/q1 from either d0/d0 or d1/d1 , when both outputs have the same transition. input clock frequency (ghz) figure 4. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature (@ v cc = 3.3 v) output voltage amplitude (mv) 0 50 100 150 200 250 300 350 400 0.5 1 1.5 2 2.5 3 0 85 c ? 40 c 25 c
NB4N527S http://onsemi.com 6 time (58 ps/div) figure 5. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 and oc48 mask (v inpp = 100 mv; input signal ddj = 14 ps) voltage (63.23 mv/div) device ddj = 10 ps r c r c 1.25 k 1.25 k 1.25 k 1.25 k 50 50 dx v tdx v tdx d x figure 6. input structure i
NB4N527S http://onsemi.com 7 gnd v cc gnd lvpecl driver dx 50 * z o = 50 z o = 50 50 * dx NB4N527S v cc v tdx gnd v cc gnd cml driver 50 * z o = 50 z o = 50 50 * NB4N527S v cc v tdx = v tdx = v cc figure 7. lvpecl interface figure 8. lvds interface v tdx = v tdx = v cc ? 2.0 v figure 9. standard 50 load cml interface gnd v cc gnd lvds driver 50 * z o = 50 z o = 50 50 * NB4N527S v cc v tdx = v tdx gnd v cc gnd hstl driver 50 * z o = 50 z o = 50 50 * NB4N527S v cc v tdx = v tdx = gnd or v dd /2 depending on driver. figure 10. hstl interface gnd v cc gnd lvcmos driver 50 * z o = 50 50 * NB4N527S v cc v tdx = v tdx = open figure 11. lvcmos interface gnd v cc gnd lvttl driver 50 * z o = 50 50 * NB4N527S v cc v tdx = open figure 12. lvttl interface v tdx dx dx v tdx v tdx dx v tdx v tdx v cc dx dx v tdx v tdx dx dx v tdx v tdx dx gnd dx v tdx v tdx dx gnd *r tin , internal input termination resistor. 2.5 k 1.5 k
NB4N527S http://onsemi.com 8 figure 13. ac reference measurement d d q q t phl t plh v inpp = v ih (d x ) ? v il (d x ) v outpp = v oh (q x ) ? v ol (q x ) figure 14. typical lvds termination for output driver and device evaluation driver device oscilloscope qd q d lvds 100 z o = 50 z o = 50 hi z probe hi z probe v ol q n v oh q n v os v od figure 15. lvds output figure 16. differential input driven single ? ended d figure 17. differential inputs driven differentially d v th v th d d v ih v il v ihmax v ilmax v ihmin v ilmin v cc v thmax v thmin gnd v th figure 18. v th diagram d d v il v ih(max) v ih v il v ih v il(min) v cmr v ee figure 19. v cmr diagram v inpp = v ihd ? v ild v cc
NB4N527S http://onsemi.com 9 ordering information device package shipping ? NB4N527Smng qfn ? 16 (pb ? free) 123 units / rail NB4N527Smnr2g qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB4N527S http://onsemi.com 10 package dimensions ??? ??? ??? case 485g ? 01 issue e 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NB4N527S/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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